A. Field of the Invention
The present invention relates to a traffic control circuit and method for multicast packet transmission, especially to a traffic control circuit and method in a network switch for reducing the traffic between the network switch and the external memories, thereby to utilize the network bandwidth more efficiently.
B. Description of the Prior Art
It is estimated that more than ten percent of the traffic in the Internet is occupied by the multicast packets, including broadcast packets. A conventional approach to process the traffic caused by the multicast packets is called "copy of packet memory". Refer to FIG. 1, the approach of "copy of packet memory" replicates the coming packets in a packet memory 12 and stores control data in a control memory 13. The number of packets and control data copied depends on the number of ports to be transferred. The network switch 11 will send a request for transmission to each output port 14. The output port 14 of the network switch 11 will transfer a multicast packet from the packet memory 12 in response to its corresponding control data stored in the control memory 13. After the transmission is complete, the memory space of the packet memory 12 and of the control memory 13 will be released. This approach is very straightforward and easy to implement. Nevertheless, it may cause lots of traffic between the network switch 11 and the external memories, especially the packet memory 12 and the control memory 13.
Another approach is called "copy of control memory". Refer to FIG. 2 for an exemplary implementation based on this approach. The network switch 21 has multiple output ports 27 for transferring packets to their destination addresses. When a multicast packet arrives, one copy of the multicast packet will be stored in the packet memory 22. The control data for each copy of multicast packets will then be stored in the control memory 23.
The control data stored the control memory 23 includes: a packet memory link list 24, a counter 25, a control pointer of a output port (or descriptor) 26. The network switch 21 will replicate the control pointer of an output port 26 to the control memory of the output port in response to the message of the forwarding port. The multicast packets stored in the packet memory 22 will not be transmitted by those output ports until the output port 27 receives a control pointer. The counter 25 is for recording the number of times for packet transmission. The output port 27 sends a copy of the multicast packet stored in the packet memory 22 to its forwarding port according to its control data stored in the control memory 23. After each packet is sent, its memory space in the control memory 23 will be released. The value of counter 25 value will also be updated. Nevertheless, its memory space in the packet memory 22 will not be released until the counter 25 expires.
Apparently, the approach of "copy of control memory" can save more network bandwidth than the approach of "copy of packet memory" because only one copy of the multicast packet is stored in the packet memory 22. Moreover, the multicast packet in the packet memory 22 will not be transferred to the output port 27 until the output port 27 receives a control pointer of the multicast packet. However, this approach is more difficult to implement than the previous one. Moreover, it may result in the insufficient bandwidth of the control memory 23.
There are several other approaches trying to improve the bandwidth of the networks. For instance, U.S. Pat. No. 5,701,437, "Dual-Memory Managing Apparatus and Method Including Prioritization of Backup and Update Operations", discloses a dual-memory managing apparatus which is connected to multiple memories and processors through a data bus such that identical data are stored in the multiple memories. The invention can prevent the degradation of processing capability of the apparatus in a memory copy mode.
In another patent, U.S. Pat. No. 5,432,908, "High Speed Buffer Management Of Share Memory Using Linked Lists And Plural Buffer Circuits For Processing Multiple Requests Concurrently", involves in using a memory which is large and fast for controlling and managing the data in the buffer, thereby to speed up the network communication speed.
On the other hand, as to the hardware controls over the buffers and stacks, U.S. Pat. No. 5,107,457, "Stack Data Cache Having A Stack Management Hardware With Internal And External Stack Pointers And Buffers For Handling Underflow And Overflow Stack", uses a stack management to control the overflow and underflow of the stack, thereby to improve the efficiency of the stacks.
Consequently, all of the above mentioned patents intend to improve the network bandwidth either by increasing the memory size, or the speed of the memory buffer, or even using fast cache memory. Basically, their improvements are based on adding additional hardware elements to achieve a desired effect with the trade-off of additional cost.